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» Scaling, Power and the Future of CMOS
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SC
2009
ACM
15 years 4 months ago
Future scaling of processor-memory interfaces
Continuous evolution in process technology brings energyefficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high ba...
Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis,...
FPGA
2006
ACM
141views FPGA» more  FPGA 2006»
15 years 1 months ago
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
Dmitri B. Strukov, Konstantin Likharev
AINA
2007
IEEE
15 years 4 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
IC3
2009
14 years 7 months ago
Multi-scale Modeling and Analysis of Nano-RFID Systems on HPC Setup
In this paper we have worked out on some the complex modeling aspects such as Multi Scale modeling, MATLAB Sugar based modeling and have shown the complexities involved in the anal...
Rohit Pathak, Satyadhar Joshi
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
15 years 6 months ago
Power switch characterization for fine-grained dynamic voltage scaling
—Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connec...
Liang Di, Mateja Putic, John Lach, Benton H. Calho...