87 search results - page 9 / 18 » Scaling Application Performance on a Cache-Coherent Multipro... |
112
click to vote
JSA
2007
14 years 11 months ago
2007
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
105
click to vote
HPCA
2006
IEEE
16 years 14 hour ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
112
click to vote
PDPTA
1996
15 years 29 days ago
1996
This paper presents pTask-- a system that allows users to automatically exploit dynamic task-level parallelism in sequential array-based C programs. The system employs compiler an...
VLDB
2001
ACM
15 years 4 months ago
2001
ACM
Recent research addressed the importance of optimizing L2 cache utilization in the design of main memory indexes and proposed the so-called cache-conscious indexes such as the CSB...
DDECS
2006
IEEE
15 years 5 months ago
2006
IEEE
—The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application...