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» Scaling Soft Processor Systems
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SIGIR
1996
ACM
15 years 6 months ago
Performance Evaluation of a Distributed Architecture for Information Retrieval
Information explosion across the Internet and elsewhere offers access to an increasing number of document collections. In order for users to e ectively access these collections, i...
Brendon Cahoon, Kathryn S. McKinley
95
Voted
IPPS
2006
IEEE
15 years 8 months ago
MegaProto/E: power-aware high-performance cluster with commodity technology
In our research project named “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, we have been developing a prototype cluster not based on ASIC or FPGA...
Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, H...
131
Voted
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 6 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
SIGMETRICS
1996
ACM
118views Hardware» more  SIGMETRICS 1996»
15 years 6 months ago
Integrating Performance Monitoring and Communication in Parallel Computers
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
Margaret Martonosi, David Ofelt, Mark Heinrich
141
Voted
CP
2008
Springer
15 years 3 months ago
An Application of Constraint Programming to Superblock Instruction Scheduling
Modern computer architectures have complex features that can only be fully taken advantage of if the compiler schedules the compiled code. A standard region of code for scheduling ...
Abid M. Malik, Michael Chase, Tyrel Russell, Peter...