860 search results - page 56 / 172 » Scaling Up Software Architecture Evaluation Processes |
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MICRO
2010
IEEE
14 years 8 months ago
2010
IEEE
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
IPPS
2002
IEEE
15 years 3 months ago
2002
IEEE
Short vector SIMD instructions on recent microprocessors, such as SSE on Pentium III and 4, speed up code but are a major challenge to software developers. We present a compiler t...
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IPPS
2003
IEEE
15 years 3 months ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
ICSE
2007
IEEE-ACM
15 years 10 months ago
2007
IEEE-ACM
Database-centric information systems are critical to the operations of large organisations. In particular, they often process a large amount of data with stringent performance req...
EUROPAR
2007
Springer
15 years 2 months ago
2007
Springer
Due to the increasing performance requirements of decoding H.264/AVC in HDTV or larger resolutions, new approaches are necessary to enable real-time processing. According to the cu...