1263 search results - page 110 / 253 » Scatter-Add in Data Parallel Architectures |
265
Voted
GLVLSI
2011
IEEE
14 years 7 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
139
Voted
SIPS
2008
IEEE
15 years 10 months ago
2008
IEEE
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
164
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SASP
2008
IEEE
15 years 10 months ago
2008
IEEE
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
130
Voted
ICDCSW
2002
IEEE
15 years 8 months ago
2002
IEEE
In the near future, there will be increasingly powerful computers in smart cards, telephones, and other information appliances. This will create a massive infrastructure composed ...
161
Voted
VIS
2005
IEEE
16 years 5 months ago
2005
IEEE
We describe OpenGL Multipipe SDK (MPK), a toolkit for scalable parallel rendering based on OpenGL. MPK provides a uniform application programming interface (API) to manage scalabl...