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HPCA
2008
IEEE
15 years 10 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
EUROPAR
2007
Springer
15 years 4 months ago
Toward Scalable Matrix Multiply on Multithreaded Architectures
We show empirically that some of the issues that affected the design of linear algebra libraries for distributed memory architectures will also likely affect such libraries for s...
Bryan Marker, Field G. Van Zee, Kazushige Goto, Gr...
IPPS
2000
IEEE
15 years 2 months ago
Reconfigurable Parallel Sorting and Load Balancing on a Beowulf Cluster: HeteroSort
HeteroSort load balances and sorts within static or dynamic networks using a conceptual torus mesh. We ported HeteroSort to a 16-node Beowulf cluster with a central switch architec...
Pamela Yang, Timothy M. Kunau, Bonnie Holte Bennet...
ISCA
2003
IEEE
114views Hardware» more  ISCA 2003»
15 years 3 months ago
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the p...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Hai...
HIPS
1998
IEEE
15 years 2 months ago
Implementing Automatic Coordination on Networks of Workstations
Distributed shared objects are a well known approach to achieve independenceof the memory model for parallel programming. The illusion of shared (global) objects is a conabstracti...
Christian Weiß, Jürgen Knopp, Hermann H...