Sciweavers

310 search results - page 8 / 62
» Scenario-based Validation of Embedded Systems
Sort
View
FDL
2007
IEEE
15 years 3 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
EMSOFT
2006
Springer
14 years 11 months ago
Reusable models for timing and liveness analysis of middleware for distributed real-time and embedded systems
Distributed real-time and embedded (DRE) systems have stringent constraints on timeliness and other properties whose assurance is crucial to correct system behavior. Formal tools ...
Venkita Subramonian, Christopher D. Gill, Cé...
IAJIT
2011
14 years 28 days ago
An RFID-based validation system for halal food
: In recent years, Muslims have depended on the Halal logo, displayed on food packaging, to indicate that the products are prepared according to Halal precepts. As laid out in the ...
Mohd Nasir, Azah Norman, Shukor Fauzi, Masliyana A...
67
Voted
ICFEM
2007
Springer
15 years 3 months ago
Machine-Assisted Proof Support for Validation Beyond Simulink
Simulink is popular in industry for modeling and simulating embedded systems. It is deficient to handle requirements of high-level assurance and timing analysis. Previously, we sh...
Chunqing Chen, Jin Song Dong, Jun Sun 0001
DAC
1998
ACM
15 years 10 months ago
Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems
An embedded system the system continuously interacts with its environment under strict timing constraints, called the external constraints, and it is important to know how these e...
Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta