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FATES
2004
Springer
13 years 11 months ago
Testing Deadlock-Freeness in Real-Time Systems: A Formal Approach
A Time Action Lock is a state of a Real-time system at which neither time can progress nor an action can occur. Time Action Locks are often seen as signs of errors in the model or ...
Behzad Bordbar, Kozo Okano
ASWEC
2007
IEEE
14 years 18 days ago
Timed Behavior Trees and Their Application to Verifying Real-Time Systems
Behavior Trees (BTs) are a graphical notation used for formalising functional requirements and have been successfully applied to several case studies. However, the notation curren...
Lars Grunske, Kirsten Winter, Robert Colvin
CODES
2008
IEEE
13 years 8 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
ATVA
2008
Springer
159views Hardware» more  ATVA 2008»
13 years 8 months ago
Component-Based Design and Analysis of Embedded Systems with UPPAAL PORT
UPPAAL PORT is a new tool for component-based design and analysis of embedded systems. It operates on the hierarchically structured continuous time component modeling language Save...
John Håkansson, Jan Carlson, Aurelien Monot,...
IFM
2009
Springer
119views Formal Methods» more  IFM 2009»
14 years 24 days ago
Parallel Processes with Real-Time and Data: The ATLANTIF Intermediate Format
Abstract. To model real-life critical systems, one needs“high-level”languages to express three important concepts: complex data structures, concurrency, and real-time. So far, ...
Jan Stöcker, Frédéric Lang, Hub...