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RTAS
2005
IEEE
15 years 3 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...
CODES
2003
IEEE
15 years 2 months ago
Accurate estimation of cache-related preemption delay
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems difficul...
Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudh...
CODES
2006
IEEE
15 years 1 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
SAMOS
2004
Springer
15 years 2 months ago
DIF: An Interchange Format for Dataflow-Based Design Tools
The dataflow interchange format (DIF) is a textual language that is geared towards capturing the semantics of graphical design tools for DSP system design. A key objective of DIF i...
Chia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz ...
LCTRTS
2009
Springer
15 years 4 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava