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DATE
2002
IEEE
123views Hardware» more  DATE 2002»
15 years 9 months ago
False Path Elimination in Quasi-Static Scheduling
We have developed a technique to compute a Quasi Static Schedule of a concurrent specification for the software partition of an embedded system. Previous work did not take into a...
G. Arrigoni, L. Duchini, Claudio Passerone, Lucian...
HPDC
2002
IEEE
15 years 9 months ago
Decoupling Computation and Data Scheduling in Distributed Data-Intensive Applications
In high energy physics, bioinformatics, and other disciplines, we encounter applications involving numerous, loosely coupled jobs that both access and generate large data sets. So...
Kavitha Ranganathan, Ian T. Foster
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
15 years 8 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
CASES
2007
ACM
15 years 8 months ago
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
Delayed branching is a technique to alleviate branch hazards without expensive hardware branch prediction mechanisms. For VLIW processors with deep pipelines and many issue slots,...
Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter
CCS
2008
ACM
15 years 6 months ago
Avoiding timing channels in fixed-priority schedulers
A practically feasible modification to fixed-priority schedulers allows to avoid timing channels despite threads having access to precise clocks. This modification is rather simpl...
Marcus Völp, Claude-Joachim Hamann, Hermann H...