Abstract—A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, highspeed interface to increase the device den...
Xiuyi Zhou, Jun Yang 0002, Yi Xu, Youtao Zhang, Ji...
T-N Plane Abstraction (E-TNPA) proposed in this paper realizes work-conserving and efficient optimal real-time scheduling on multiprocessors relative to the original T-N Plane Ab...
— Failure-Rate Minimization is becoming one of the major design issues in wireless sensor network (WSN) architecture due to multiple available Functional-units (FUs). There is a ...
This paper investigates the scheduling of mixed-parallel applications, which exhibit both task and data parallelism, in advance reservations settings. Both the problem of minimizi...
— A control-plane architecture for supporting advance reservation of dedicated bandwidth channels on a switched network infrastructure is described including the front-end web in...
Nageswara S. V. Rao, Qishi Wu, Song Ding, Steven M...