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MSS
2003
IEEE
113views Hardware» more  MSS 2003»
15 years 10 months ago
Design and Implementation of Multiple Addresses Parallel Transmission Architecture for Storage Area Network
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...
Bin Meng, Patrick B. T. Khoo, T. C. Chong
ICCAD
1996
IEEE
106views Hardware» more  ICCAD 1996»
15 years 9 months ago
Heterogeneous built-in resiliency of application specific programmable processors
Abstract - Using the exibility provided by multiple functionalities we have developed a new approach for permanent fault-tolerance: Heterogeneous BuiltIn-Resiliency (HBIR). HBIR p...
Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
FAW
2010
Springer
232views Algorithms» more  FAW 2010»
15 years 6 months ago
Recognizing d-Interval Graphs and d-Track Interval Graphs
A d-interval is the union of d disjoint intervals on the real line. A d-track interval is the union of d disjoint intervals on d disjoint parallel lines called tracks, one interval...
Minghui Jiang
ALDT
2009
Springer
172views Algorithms» more  ALDT 2009»
15 years 11 months ago
On Multi-dimensional Envy-Free Mechanisms
Traditional performance analysis of approximation algorithms considers overall performance, while economic fairness analysis focuses on the individual performance each user receiv...
Ahuva Mu'alem
FSKD
2005
Springer
143views Fuzzy Logic» more  FSKD 2005»
15 years 10 months ago
Energy Efficient Dynamic Cluster Based Clock Synchronization for Wireless Sensor Network
Core operations (e.g. TDMA scheduler, synchronized sleep period, data aggregation) of many proposed protocols for different layer of sensor network necessitate clock synchronizatio...
Md. Mamun-Or-Rashid, Choong Seon Hong, Jinsung Cho