3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...
Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. J...
Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class p...
Inspired by emerging multi-core computer architectures, in this paper we present MT CLOSED, a multi-threaded algorithm for frequent closed itemset mining (FCIM). To the best of ou...
In the context of Intelligent Transportation Systems based on driverless vehicles, one important issue is the passing of a crossroads. This paper presents a supervised reservation ...