Sciweavers

3563 search results - page 588 / 713
» Scheduling Algorithms for Procrastinators
Sort
View
ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
15 years 8 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
158
Voted
ICCAD
1994
IEEE
112views Hardware» more  ICCAD 1994»
15 years 8 months ago
Selecting partial scan flip-flops for circuit partitioning
This paper presents a new method of selecting scan ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
Toshinobu Ono
148
Voted
ICDE
1994
IEEE
87views Database» more  ICDE 1994»
15 years 8 months ago
Implementing Calendars and Temporal Rules in Next Generation Databases
In applications like nancial trading, scheduling, manufacturing and process control, time based predicates in queries and rules are very important. There is also a need to de ne ...
Rakesh Chandra, Arie Segev, Michael Stonebraker
ISTCS
1993
Springer
15 years 8 months ago
The Minimum Reservation Rate Problem in Digital Audio/Video Systems
d Abstract) David P. Anderson Nimrod Megiddoy Moni Naorz April 1993 The \Minimum Reservation Rate Problem" arises in distributed systems for handling digital audio and video d...
Nimrod Megiddo, Moni Naor, David P. Anderson
CAV
2007
Springer
212views Hardware» more  CAV 2007»
15 years 8 months ago
A Tutorial on Satisfiability Modulo Theories
Abstract. Solvers for satisfiability modulo theories (SMT) check the satisfiability of first-order formulas containing operations from various theories such as the Booleans, bit-ve...
Leonardo Mendonça de Moura, Bruno Dutertre,...