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» Scheduling and Binding Algorithms for High-Level Synthesis
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127
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ISSS
2002
IEEE
176views Hardware» more  ISSS 2002»
15 years 10 months ago
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
DATE
1998
IEEE
109views Hardware» more  DATE 1998»
15 years 9 months ago
Cross-Level Hierarchical High-Level Synthesis
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
Oliver Bringmann, Wolfgang Rosenstiel
173
Voted
DATE
2003
IEEE
137views Hardware» more  DATE 2003»
15 years 10 months ago
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branche...
Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexa...
DATE
2002
IEEE
105views Hardware» more  DATE 2002»
15 years 10 months ago
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
Chunhong Chen, Majid Sarrafzadeh
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
15 years 11 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie