51 search results - page 5 / 11 » Scheduling and Binding Algorithms for High-Level Synthesis |
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...
ISLPED
1995
ACM
15 years 1 months ago
1995
ACM
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...
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Voted
ASPDAC
1995
ACM
15 years 1 months ago
1995
ACM
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
ISSS
1995
IEEE
15 years 1 months ago
1995
IEEE
Decisions taken at the earliest steps of the design process may have a significantimpact on the characteristics of the final implementation. This paper illustrates how power con...
ICCD
2002
IEEE
2002
IEEE
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
15 years 6 months ago
A circuit or circuit component that does not contain any spurious switching activity, i.e., activity that is not required by its specified functionality, is called perfectly power...