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» Scheduling and memory requirements analysis with AADL
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ASPLOS
2010
ACM
15 years 4 months ago
Addressing shared resource contention in multicore processors via scheduling
Contention for shared resources on multicore processors remains an unsolved problem in existing systems despite significant research efforts dedicated to this problem in the past...
Sergey Zhuravlev, Sergey Blagodurov, Alexandra Fed...
EUROPAR
1997
Springer
15 years 1 months ago
Modulo Scheduling with Cache Reuse Information
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
Chen Ding, Steve Carr, Philip H. Sweany
ICIP
2006
IEEE
15 years 11 months ago
Autonomous Detection of Dust Devils and Clouds on Mars
Acquisition of science in space applications is shifting from teleoperated gathering to an automated on-board analysis with improvements in the use of on-board memory, CPU, bandwi...
Alex Fukunaga, Andres Castano, Jeffrey J. Biesiade...
92
Voted
JUCS
2000
120views more  JUCS 2000»
14 years 9 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
ICS
1999
Tsinghua U.
15 years 1 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...