46 search results - page 6 / 10 » Scheduling and memory requirements analysis with AADL |
CODES
2007
IEEE
15 years 3 months ago
2007
IEEE
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
92
Voted
DAC
2002
ACM
15 years 10 months ago
2002
ACM
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
ECRTS
2010
IEEE
14 years 10 months ago
2010
IEEE
Schedulability analysis for hard real-time systems requires bounds on the execution times of its tasks. To obtain useful bounds in the presence of caches, static timing analyses mu...
81
Voted
CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
JSSPP
2005
Springer
15 years 3 months ago
2005
Springer
Irregular and iterative I/O-intensive jobs need a different approach from parallel job schedulers. The focus in this case is not only the processing requirements anymore: memory, ...