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» Scheduling and memory requirements analysis with AADL
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74
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CODES
2003
IEEE
15 years 2 months ago
Accurate estimation of cache-related preemption delay
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems difficul...
Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudh...
115
Voted
SAMOS
2004
Springer
15 years 2 months ago
DIF: An Interchange Format for Dataflow-Based Design Tools
The dataflow interchange format (DIF) is a textual language that is geared towards capturing the semantics of graphical design tools for DSP system design. A key objective of DIF i...
Chia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz ...
ICSM
2003
IEEE
15 years 2 months ago
DART: A Framework for Regression Testing "Nightly/daily Builds" of GUI Applications
“Nightly/daily building and smoke testing” have become widespread since they often reveal bugs early in the software development process. During these builds, software is comp...
Atif M. Memon, Ishan Banerjee, Nada Hashmi, Adithy...
ECRTS
2010
IEEE
14 years 10 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller
ICPPW
2006
IEEE
15 years 3 months ago
Model-Based OpenMP Implementation of a 3D Facial Pose Tracking System
Abstract— Most image processing applications are characterized by computation-intensive operations, and high memory and performance requirements. Parallelized implementation on s...
Sankalita Saha, Chung-Ching Shen, Chia-Jui Hsu, Ga...