43 search results - page 2 / 9 » Scheduling and resource binding for low power |
GLVLSI
1998
IEEE
13 years 10 months ago
1998
IEEE
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...
ISCAS
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V,
CODES
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...