182 search results - page 32 / 37 » Scheduling complex streaming applications on the Cell proces... |
78
Voted
HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
Allowing loads to issue out-of-order with respect to earlier unresolved store addresses is very important for extracting parallelism in large-window superscalar processors. Blindl...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
PLDI
2012
ACM
13 years 2 days ago
2012
ACM
While graphics processing units (GPUs) provide low-cost and efficient platforms for accelerating high performance computations, the tedious process of performance tuning required...
IJPP
2006
14 years 9 months ago
2006
Abstract. In order to address the problems faced in the wireless communications domain, picoChip has devised the picoArrayTM . The picoArrayTM is a tiled-processor architecture, co...
102
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ASPLOS
2010
ACM
15 years 27 days ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...