221 search results - page 11 / 45 » Scheduling instruction effects for a statically pipelined pr... |
119
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RTAS
2008
IEEE
15 years 4 months ago
2008
IEEE
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...
75
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MICRO
1999
IEEE
15 years 2 months ago
1999
IEEE
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
JSA
2008
14 years 10 months ago
2008
Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating arch...
IEEEPACT
1999
IEEE
15 years 2 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
111
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ISCA
1992
IEEE
15 years 2 months ago
1992
IEEE
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...