221 search results - page 13 / 45 » Scheduling instruction effects for a statically pipelined pr... |
MICRO
1995
IEEE
15 years 1 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
DAC
2002
ACM
15 years 11 months ago
2002
ACM
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...
LCTRTS
2007
Springer
15 years 4 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
DAC
2006
ACM
15 years 10 days ago
2006
ACM
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
MICRO
2003
IEEE
15 years 3 months ago
2003
IEEE
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...