221 search results - page 14 / 45 » Scheduling instruction effects for a statically pipelined pr... |
95
Voted
MICRO
1994
IEEE
15 years 2 months ago
1994
IEEE
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
101
Voted
ISCA
2003
IEEE
15 years 3 months ago
2003
IEEE
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
65
Voted
ICCD
2003
IEEE
15 years 7 months ago
2003
IEEE
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
108
click to vote
ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
APCSAC
2004
IEEE
15 years 2 months ago
2004
IEEE
Abstract. While the fetch unit has been identified as one of the major bottlenecks of Simultaneous Multithreading architecture, several fetch schemes were proposed by prior works t...