221 search results - page 16 / 45 » Scheduling instruction effects for a statically pipelined pr... |
102
click to vote
TCAD
2002
14 years 10 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
CF
2004
ACM
15 years 3 months ago
2004
ACM
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
CF
2005
ACM
15 years 11 days ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
83
Voted
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Simultaneous Multithreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with longlatency st...
RTSS
2002
IEEE
15 years 3 months ago
2002
IEEE
Simultaneous multithreading (SMT) improves processor throughput by processing instructions from multiple threads each cycle. This is the first work to explore soft real-time sche...