221 search results - page 17 / 45 » Scheduling instruction effects for a statically pipelined pr... |
101
click to vote
CASES
2005
ACM
15 years 12 days ago
2005
ACM
Customisable embedded processors are becoming available on the market, thus making it possible for designers to speed up execution of applications by using Application-specific F...
MICRO
1997
IEEE
15 years 2 months ago
1997
IEEE
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
ICS
2005
Tsinghua U.
15 years 3 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
217
click to vote
ICDE
1999
IEEE
15 years 11 months ago
1999
IEEE
We present parallel algorithms for building decision-tree classifiers on shared-memory multiprocessor (SMP) systems. The proposed algorithms span the gamut of data and task parall...
86
Voted
TVLSI
2002
14 years 10 months ago
2002
We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea ...