221 search results - page 19 / 45 » Scheduling instruction effects for a statically pipelined pr... |
129
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ECRTS
2006
IEEE
15 years 4 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
CONCURRENCY
2006
14 years 10 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
CASES
2006
ACM
15 years 2 months ago
2006
ACM
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
72
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HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Serializing instructions (SIs), such as writes to control registers, have many complex dependencies, and are difficult to execute out-of-order (OoO). To avoid unnecessary complexi...
143
Voted
FDTC
2011
Springer
13 years 10 months ago
2011
Springer
Abstract—The literature about fault analysis typically describes fault injection mechanisms, e.g. glitches and lasers, and cryptanalytic techniques to exploit faults based on som...