221 search results - page 20 / 45 » Scheduling instruction effects for a statically pipelined pr... |
IEEEPACT
2007
IEEE
15 years 4 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
111
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ASPLOS
2008
ACM
15 years 14 days ago
2008
ACM
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
118
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IEEEPACT
2002
IEEE
15 years 3 months ago
2002
IEEE
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
JEC
2006
14 years 10 months ago
2006
Many applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). In our previous work, we proposed a ...
112
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DAC
2007
ACM
15 years 11 months ago
2007
ACM
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...