221 search results - page 21 / 45 » Scheduling instruction effects for a statically pipelined pr... |
101
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CGO
2004
IEEE
15 years 2 months ago
2004
IEEE
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...
PPOPP
1990
ACM
15 years 2 months ago
1990
ACM
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
EUROPAR
1999
Springer
15 years 2 months ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
107
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RSP
2000
IEEE
15 years 2 months ago
2000
IEEE
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
MICRO
2003
IEEE
15 years 3 months ago
2003
IEEE
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...