221 search results - page 23 / 45 » Scheduling instruction effects for a statically pipelined pr... |
GLVLSI
2002
IEEE
15 years 3 months ago
2002
IEEE
Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). ...
LCPC
2004
Springer
15 years 3 months ago
2004
Springer
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
119
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LCTRTS
2000
Springer
15 years 2 months ago
2000
Springer
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
98
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EUROPAR
1997
Springer
15 years 2 months ago
1997
Springer
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
105
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ICCD
2005
IEEE
15 years 7 months ago
2005
IEEE
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...