221 search results - page 26 / 45 » Scheduling instruction effects for a statically pipelined pr... |
SAMOS
2007
Springer
15 years 4 months ago
2007
Springer
When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however...
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
96
Voted
DATE
2010
IEEE
15 years 3 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
SIGMOD
2004
ACM
15 years 10 months ago
2004
ACM
We present new algorithms on commodity graphics processors to perform fast computation of several common database operations. Specifically, we consider operations such as conjunct...
108
Voted
ISCA
2003
IEEE
15 years 3 months ago
2003
IEEE
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...