221 search results - page 27 / 45 » Scheduling instruction effects for a statically pipelined pr... |
POPL
2010
ACM
15 years 7 months ago
2010
ACM
Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class p...
CASES
2004
ACM
15 years 3 months ago
2004
ACM
A coarse-grain multithreaded processor can effectively hide long memory latencies by quickly switching to an alternate task when the active task issues a memory request, improving...
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CGO
2003
IEEE
15 years 3 months ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
ISCA
2005
IEEE
15 years 4 months ago
2005
IEEE
This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...
ISCA
2000
IEEE
15 years 2 months ago
2000
IEEE
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...