221 search results - page 28 / 45 » Scheduling instruction effects for a statically pipelined pr... |
74
Voted
SAC
2004
ACM
15 years 3 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
CGO
2004
IEEE
15 years 2 months ago
2004
IEEE
Predicated execution enables the removal of branches by converting segments of branching code into sequences of conditional operations. An important side effect of this transforma...
SAC
2008
ACM
14 years 10 months ago
2008
ACM
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test rout...
102
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HPCA
2003
IEEE
15 years 10 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
TVLSI
2008
14 years 10 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...