221 search results - page 29 / 45 » Scheduling instruction effects for a statically pipelined pr... |
ISLPED
2006
ACM
15 years 4 months ago
2006
ACM
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
ISCA
2011
IEEE
14 years 2 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
APCSAC
2005
IEEE
15 years 4 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
ISPAN
1999
IEEE
15 years 2 months ago
1999
IEEE
To minimize the execution time of an iterative application in a heterogeneous parallel computing environment, an appropriate mapping scheme is needed for matching and scheduling th...
85
Voted
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...