221 search results - page 31 / 45 » Scheduling instruction effects for a statically pipelined pr... |
103
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DAC
2010
ACM
14 years 10 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
102
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ISCAS
2005
IEEE
15 years 4 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
JILP
2000
14 years 10 months ago
2000
In today's wide-issue processors, even small branch-misprediction rates introduce substantial performance penalties. Worse yet, inadequate branch prediction creates a bottlen...
PDPTA
2003
14 years 11 months ago
2003
This paper presents the effectiveness of an interactive support facility to tune processor allocation of data-driven realtime programs on CUE (Coordinating Users’ requirements an...
LCTRTS
2009
Springer
15 years 5 months ago
2009
Springer
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...