221 search results - page 32 / 45 » Scheduling instruction effects for a statically pipelined pr... |
ISCA
2006
IEEE
15 years 4 months ago
2006
IEEE
The key to high performance in Simultaneous Multithreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distributio...
RTAS
2005
IEEE
15 years 4 months ago
2005
IEEE
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
SAMOS
2010
Springer
14 years 8 months ago
2010
Springer
OpenCL is a programming language standard which enables the programmer to express the application by structuring its computation as kernels. The OpenCL compiler is given the explic...
MICRO
2003
IEEE
15 years 3 months ago
2003
IEEE
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
RTSS
1999
IEEE
15 years 2 months ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...