221 search results - page 36 / 45 » Scheduling instruction effects for a statically pipelined pr... |
ISCA
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an instruction will produce th...
119
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VEE
2010
ACM
15 years 5 months ago
2010
ACM
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
74
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IPPS
2005
IEEE
15 years 4 months ago
2005
IEEE
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...
ICASSP
2008
IEEE
15 years 4 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
MICRO
1998
IEEE
15 years 2 months ago
1998
IEEE
Load latency remains a significant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Pred...