221 search results - page 40 / 45 » Scheduling instruction effects for a statically pipelined pr... |
ASPLOS
2004
ACM
15 years 3 months ago
2004
ACM
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
105
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LCTRTS
2005
Springer
15 years 3 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
CASES
2006
ACM
15 years 2 months ago
2006
ACM
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
PLDI
2005
ACM
15 years 3 months ago
2005
ACM
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
DAC
2002
ACM
15 years 11 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...