221 search results - page 42 / 45 » Scheduling instruction effects for a statically pipelined pr... |
RTSS
2006
IEEE
15 years 4 months ago
2006
IEEE
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
ISCA
1998
IEEE
15 years 2 months ago
1998
IEEE
As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the...
LCPC
2000
Springer
15 years 1 months ago
2000
Springer
This paper proposes a simple and efficient implementation method for a hierarchical coarse grain task parallel processing scheme on a SMP machine. OSCAR multigrain parallelizing c...
LCTRTS
2007
Springer
15 years 4 months ago
2007
Springer
In the design of real-time and embedded systems, it is important to establish a bound on the worst-case execution time (WCET) of programs to assure via schedulability analysis tha...
SIGSOFT
2005
ACM
15 years 11 months ago
2005
ACM
We develop a method for matching dynamic histories of program executions of two program versions. The matches produced can be useful in many applications including software piracy...