221 search results - page 5 / 45 » Scheduling instruction effects for a statically pipelined pr... |
102
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APCSAC
2001
IEEE
15 years 2 months ago
2001
IEEE
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
TVLSI
2002
14 years 10 months ago
2002
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
MICRO
1997
IEEE
15 years 1 months ago
1997
IEEE
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
113
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ASPLOS
2004
ACM
15 years 3 months ago
2004
ACM
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
ISCA
1997
IEEE
15 years 2 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...