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97
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VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 1 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
GLOBECOM
2009
IEEE
15 years 7 months ago
Maximizing Lifetime of Sensor-Target Surveillance in Wireless Sensor Networks
—The paper addresses the maximal lifetime problem in sensor-target surveillance networks. Given a set of sensors and targets in an Euclidean plane, each sensor can watch all targ...
Hai Liu, Xiaowen Chu, Yiu-Wing Leung, Xiaohua Jia,...
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
15 years 2 months ago
On multiple-voltage high-level synthesis using algorithmic transformations
— This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by...
Hsueh-Chih Yang, Lan-Rong Dung
HPDC
2010
IEEE
15 years 1 months ago
A hybrid Markov chain model for workload on parallel computers
This paper proposes a comprehensive modeling architecture for workloads on parallel computers using Markov chains in combination with state dependent empirical distribution functi...
Anne Krampe, Joachim Lepping, Wiebke Sieben
104
Voted
EAAI
2008
101views more  EAAI 2008»
15 years 23 days ago
A global constraint for total weighted completion time for cumulative resources
The criterion of total weighted completion time occurs as a sub-problem of combinatorial optimization problems in such diverse areas as scheduling, container loading and storage a...
András Kovács, J. Christopher Beck