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DATE
2010
IEEE
110views Hardware» more  DATE 2010»
15 years 6 months ago
Enabling efficient post-silicon debug by clustering of hardware-assertions
—Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the ...
Mohammad Hossein Neishaburi, Zeljko Zilic
95
Voted
DAC
2009
ACM
15 years 5 months ago
GPU-based parallelization for fast circuit optimization
The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit opt...
Yifang Liu, Jiang Hu
DATE
1999
IEEE
105views Hardware» more  DATE 1999»
15 years 5 months ago
Identification and Exploitation of Symmetries in DSP Algorithms
In many algorithms, particularly those in the DSP domain, certain forms of symmetry can be observed. To efficiently implement such algorithms, it is often possible to exploit thes...
C. A. J. van Eijk, E. T. A. F. Jacobs, Bart Mesman...
ICSM
1999
IEEE
15 years 5 months ago
Test Case Prioritization: An Empirical Study
Test case prioritization techniques schedule test cases for execution in an order that attempts to maximize some objective function. A variety of objective functions are applicabl...
Gregg Rothermel, Roland H. Untch, Chengyun Chu, Ma...
121
Voted
CODES
1996
IEEE
15 years 5 months ago
Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications
The design of multi-dimensional systems using hardware/software codesign allows a significant improvement in the development cycle. This paper presents a technique that enables a ...
Michael Sheliga, Nelson L. Passos, Edwin Hsing-Mea...