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» Scheduling techniques for media-on-demand
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116
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VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
16 years 1 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...
106
Voted
QEST
2009
IEEE
15 years 7 months ago
On the Impact of Modelling Choices for Distributed Information Spread
—We consider a distributed shuffling algorithm for sharing data in a distributed network. Nodes executing the algorithm periodically contact each other and exchange data. The be...
Rena Bakhshi, Ansgar Fehnker
95
Voted
DSN
2005
IEEE
15 years 6 months ago
A Wavefront Parallelisation of CTMC Solution Using MTBDDs
In this paper, we present a parallel implementation for the steady-state analysis of continuous-time Markov chains (CTMCs). This analysis is performed via solution of a linear equ...
Yi Zhang, David Parker, Marta Z. Kwiatkowska
HPCA
2005
IEEE
15 years 6 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
15 years 6 months ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...