—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
The e ective design of composite dependable and real-time protocols entails demonstrating their proof of correctness and, in practice, the e cient delivery of services. We focus o...
—Adapting transmission parameters to the future channel state is an appealing approach to improve efficiency in wireless communication. Adaptation requires predicting the chann...
Ana Aguiar, Holger Karl, Adam Wolisz, Horst Miesme...
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
William Jalby, Christophe Lemuet, Sid Ahmed Ali To...
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability...