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DATE
1999
IEEE
127views Hardware» more  DATE 1999»
15 years 4 months ago
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
89
Voted
ISCA
2007
IEEE
114views Hardware» more  ISCA 2007»
15 years 6 months ago
Matrix scheduler reloaded
From multiprocessor scale-up to cache sizes to the number of reorder-buffer entries, microarchitects wish to reap the benefits of more computing resources while staying within po...
Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, ...
EDBTW
2010
Springer
15 years 5 months ago
Declarative scheduling in highly scalable systems
In modern architectures based on Web Services or Cloud Computing, a very large number of user requests arrive concurrently and has to be scheduled for execution constrained by cor...
Christian Tilgner
IPPS
2002
IEEE
15 years 5 months ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
84
Voted
ECRTS
1999
IEEE
15 years 4 months ago
Dynamic value-density for scheduling real-time systems
Scheduling decisions in time-critical systems are very difficult, due to the vast number of systems' parameters and tasks' attributes involved in such decisions. Due to ...
Saud A. Aldarmi, Alan Burns