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EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
15 years 7 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
154
Voted
ICCAD
1995
IEEE
180views Hardware» more  ICCAD 1995»
15 years 7 months ago
Design based analog testing by Characteristic Observation Inference
In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antrei...
ISLPED
1995
ACM
193views Hardware» more  ISLPED 1995»
15 years 7 months ago
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
ASPDAC
2008
ACM
151views Hardware» more  ASPDAC 2008»
15 years 6 months ago
High performance current-mode differential logic
This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage ...
Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Ch...
CDC
2008
IEEE
192views Control Systems» more  CDC 2008»
15 years 6 months ago
Distributed coordination algorithms for multiple fractional-order systems
Abstract-- This paper studies distributed coordination algorithms for multiple fractional-order systems over a directed communication graph. A general fractional-order consensus mo...
Yongcan Cao, Yan Li, Wei Ren, Yangquan Chen