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DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 6 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
IWOMP
2009
Springer
15 years 7 months ago
Evaluating OpenMP 3.0 Run Time Systems on Unbalanced Task Graphs
The UTS benchmark is used to evaluate task parallelism in OpenMP 3.0 as implemented in a number of recently released compilers and run-time systems. UTS performs parallel search of...
Stephen Olivier, Jan Prins
105
Voted
ICTAC
2005
Springer
15 years 6 months ago
Stochastic Analysis of Graph Transformation Systems: A Case Study in P2P Networks
In distributed and mobile systems with volatile bandwidth and fragile connectivity, non-functional aspects like performance and reliability become more and more important. To forma...
Reiko Heckel
111
Voted
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 6 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
138
Voted
ICML
2007
IEEE
16 years 1 months ago
Entire regularization paths for graph data
Graph data such as chemical compounds and XML documents are getting more common in many application domains. A main difficulty of graph data processing lies in the intrinsic high ...
Koji Tsuda