11 search results - page 2 / 3 » Secure Design Flow for Asynchronous Multi-valued Logic Circu... |
89
Voted
DAC
2005
ACM
15 years 5 days ago
2005
ACM
1 This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circui...
80
Voted
CHES
2006
Springer
15 years 1 months ago
2006
Springer
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...
84
Voted
CHES
2006
Springer
15 years 1 months ago
2006
Springer
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
76
Voted
CODES
2007
IEEE
15 years 4 months ago
2007
IEEE
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
111
Voted
CASES
2008
ACM
15 years 6 days ago
2008
ACM
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...