1210 search results - page 121 / 242 » Secure Logic Synthesis |
ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
Ordered Binary Decision Diagrams (BDDs) are frequently used in logic synthesis. In this paper a new exact BDD minimization algorithm is presented, which is based on state space se...
ISVLSI
2002
IEEE
15 years 2 months ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...
DFT
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
VTS
1998
IEEE
15 years 2 months ago
1998
IEEE
A fast fault-tolerant controller structure is presented, which is capable of recovering from transient faults by performing a rollback operation in hardware. The proposed fault-to...
BIRTHDAY
2008
Springer
14 years 12 months ago
2008
Springer
Abstract. We survey some of the main results regarding the complexity and expressive power of Live Sequence Charts (LSCs). We first describe the two main semantics given to LSCs: a...