1210 search results - page 155 / 242 » Secure Logic Synthesis |
131
Voted
AAI
2004
15 years 3 months ago
2004
We are interested in applying model checking techniques to the verification of communication protocols which require safe communication. Typically, in such scenarios, one desires ...
123
Voted
DAC
2001
ACM
16 years 4 months ago
2001
ACM
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
108
Voted
DAC
2003
ACM
16 years 4 months ago
2003
ACM
Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...
178
Voted
DAC
2006
ACM
16 years 4 months ago
2006
ACM
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
126
Voted
ICCAD
2006
IEEE
16 years 12 days ago
2006
IEEE
The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). State-of-the-art methods use simulat...